1. Field of the Invention
This invention relates to an information processing system, and more particularly, to an information processing system with an improved arithmetic and control units.
The operation of a digital computer is classified into two groups. One is a synchronous operation in which data are transferred between the respective elements in synchronism with clock pulses and the operations of the respective elements are also carried out in synchronism with the clock pulses. The other is called an asynchronous operation. This invention relates to the synchronous operation, as mentioned previously.
2. Description of the Prior Art
In the conventional synchronous information processing system various clock pulses, such as multiphase-multicycle (or single cycle) pulses and single-phase-multicycle pulses, have been used in order to avoid adverse effects of the differences in time period needed for actuation of the memory unit, for data transmission through the respective circuits or elements employed in the arithmetic unit and/or control unit, and for data processing. In other words, a plurality of multiphase clock pulses having their phases shifted from each other are generated corresponding to a plurality of timings for the control of operations of the respective stages in accordance with the speeds of the respective circuit operations. The operation is performed in such a manner for instance, that a control signal for opening a gate is generated at the timing of a first clock pulse, the setting of the data passed through the gate in a register is achieved at the timing of a second clock pulse, the renewal of an address register for generating the following control signal is achieved at the timing of a third clock pulse, and the generation of a stable control signal is achieved again at the timing of the following first clock pulse. Alteratively, the operation may be in such a manner that in the memory unit, an address of a core memory is stored in an address register at the timing of the first clock pulse, then this address is designated for the core memory to set the core memory for a data register corresponding to this address at the timing of the second clock pulse, and the contents of this data register are re-written in a core area corresponding to the same address and simultaneously therewith these data are transferred to an arithmetic unit at the timing of the third clock pulse.
In these conventional systems, closed data paths are provided in the arithmetic unit and the control unit, respectively. In each of the closed data paths, a plurality of stages of memory means are employed, to which the clock pulses having different timings from each other are applied. Consequently, not only the data processing time of the processor is long, but also a great many circuits or circuit elements are required which complicate the data processor as a whole. In a synchronous computer, the complexity and operational speed of each unit are determined by how many periods of clock pulses and how many different kinds of clock pulses are required for finishing an operation responsive to the control signals. Therefore, if an operation responsive to the control signals can be finished during a minimum number of cycles of clock pulses and a minimum number of different kinds of clock pulses while generating the next control signals within the same period of time, then a high operational speed can be attained with a more simple construction. Optimally, if control signals are generated, which have a duration of only one cycle and which are renewed in each cycle so that each unit may finish the operation responsive to the control signals within one cycle, then the highest speed would be obtained with a simple construction.